Printed circuit boards (hereinafter also referred to as PCBs), chip carriers, and the like (all referred to herein as “circuitized substrates”) are typically produced in laminate form in which several layered dielectric and conductive material members (laminates) are bonded together using conventional lamination processing involving relatively high temperatures and pressures. The conductive layers, typically of thin copper, are usually used in the formed substrate for providing electrical connections to and among various devices located on the surface of the substrate, examples of such devices being integrated circuits (semiconductor chips) and discrete passive devices, such as capacitors, resistors, inductors, and the like. Typically, these discrete passive devices occupy a high percentage of the surface area of the completed multi-layered substrate, which is obviously undesirable from a future design perspective due to the ever-present demand for miniaturization.
There have been various efforts to include multiple functions (e.g., resistors, capacitors and the like) within a single component adapted for being mounted on a substrate (e.g., PCB) in an attempt to increase the available upper substrate surface area (also often referred to as “real estate”). When passive devices are in such a configuration, these are often referred to collectively and individually as integral passive devices or the like, meaning that the functions are integrated into the singular component. Because of such external positioning, these components still utilize, albeit less than if in singular form, valuable board real estate. In response, there have been efforts to embed discrete passive components within the board. When so positioned, such components are also referred to as “embedded” passive components. A capacitor designed for disposition within (between selected layers of) a PCB substrate may thus be referred to as an embedded integral passive component, or, more simply, an embedded capacitor. Such a capacitor thus provides internal capacitance. The result of this internal positioning is that it is unnecessary to also position such devices externally on the PCB's outer surface(s), thus saving valuable PCB real estate.
For an established capacitor area, two approaches are known for increasing the planar capacitance (capacitance/area) of an internal capacitor. In one such approach, higher dielectric constant materials can be used, while in a second, the thickness of the dielectric can be reduced. These constraints are reflected in the following formula, known in the art, for capacitance per area:C/A=(Dielectric Constant of Laminate×Dielectric Constant in Vacuum/Dielectric Thickness)where: C is the capacitance and A is the capacitor's area. Additional formulae are provided herein with respect to defining capacitance values for the structures formed herein.
As mentioned above, there have been previous attempts to provide internal capacitance and other internal conductive structures, components or devices (one good example being internal semiconductor chips) within circuitized substrates such as PCBs, some of these including the use of nano-powders. The cited application Ser. No. 11/031,085 and U.S. Pat. No. 7,384,856 also define such approaches. Some of the patents and some pending applications cited above mention the use of various materials for providing desired capacitance levels. With respect to the following patents, some mention or suggest problems associated with the methods and resulting materials used to do so.
None of the methods of the prior art produce embedded capacitors having as high a capacitive volumetric efficiency as the method of the present invention. In other words, higher capacitance capacitors may be formed in smaller volumes within the laminated printed circuit board than has heretofore been possible.
None of the patents and published patent applications, taken singly, or in any combination are seen to teach or suggest the novel methods forming embedded, multilayer capacitors of the present invention.